Scan architectures are commonly used to test digital circuitry in integrated circuits (IC). In automotive devices that must adhere to strict safety regulations, scan chains may be used to perform self-test each time a device is powered on, such as when a vehicle is started. Additional testing may be performed within defined time periods during operation of a device in order to assure correct operation. Self-test time governs the total boot-up time and it should also fit within a specified application time interval during application mode operation. The self-test time is mainly governed by frequency of operation. For instance, consider an IC device with max frequency of 100 MHz and functional worst case switching activity of 25%. In this case, running the scan (1100 pattern sequence) at 100 MHz may cause 50% switching activity and thereby doubles the power consumption. Hence in this case, the max scan frequency may be limited to 50 MHz in order not to exceed power dissipation limits. For a given pattern set, running the tests at 50 MHz as opposed to 100 MHz may double the test-time and application time.
Other features of the present embodiments will be apparent from the accompanying drawings and from the detailed description that follows.